- Reworked IDT initialization to register all 32 CPU exception handlers (ISR 0-31)
and 16 hardware interrupt handlers (IRQ 0-15, mapped to IDT entries 32-47).
- Created assembly stubs in interrupts.S using macros for ISRs with and without
error codes, plus IRQ stubs. All route through a common stub that saves
registers, loads kernel data segment, and calls the C handler.
- Added isr.c with a unified interrupt dispatcher that handles both exceptions
(halts on fault) and hardware IRQs (sends EOI via PIC).
- Implemented PIC (8259) driver in pic.c with full initialization sequence that
remaps IRQ 0-7 to IDT 32-39 and IRQ 8-15 to IDT 40-47. Includes mask/unmask
and EOI support.
- Extracted port I/O primitives (inb, outb, io_wait) into port_io.h header for
reuse across drivers.
- Kernel now initializes PIC after IDT and enables interrupts with STI.
This commit adds GDT initialization with proper code/data segments and reloads CS.
It also adds the initial IDT structure and loads an empty IDT.
Build configuration updated to disable SSE/MMX to prevent compiler generation of unsupported instructions in early boot.
