f1923fdbcf
- Reworked IDT initialization to register all 32 CPU exception handlers (ISR 0-31) and 16 hardware interrupt handlers (IRQ 0-15, mapped to IDT entries 32-47). - Created assembly stubs in interrupts.S using macros for ISRs with and without error codes, plus IRQ stubs. All route through a common stub that saves registers, loads kernel data segment, and calls the C handler. - Added isr.c with a unified interrupt dispatcher that handles both exceptions (halts on fault) and hardware IRQs (sends EOI via PIC). - Implemented PIC (8259) driver in pic.c with full initialization sequence that remaps IRQ 0-7 to IDT 32-39 and IRQ 8-15 to IDT 40-47. Includes mask/unmask and EOI support. - Extracted port I/O primitives (inb, outb, io_wait) into port_io.h header for reuse across drivers. - Kernel now initializes PIC after IDT and enables interrupts with STI.
96 lines
2.5 KiB
C
96 lines
2.5 KiB
C
#include "pic.h"
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#include "port_io.h"
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#define PIC1_COMMAND 0x20
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#define PIC1_DATA 0x21
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#define PIC2_COMMAND 0xA0
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#define PIC2_DATA 0xA1
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#define ICW1_ICW4 0x01 /* ICW4 (not) needed */
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#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
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#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
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#define ICW1_INIT 0x10 /* Initialization - required! */
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#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
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#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
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#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
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#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
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#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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#define PIC_EOI 0x20
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void pic_send_eoi(uint8_t irq)
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{
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if(irq >= 8)
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outb(PIC2_COMMAND, PIC_EOI);
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outb(PIC1_COMMAND, PIC_EOI);
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}
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/*
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reinitialize the PIC controllers, giving them specified vector offsets
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rather than 8h and 70h, as configured by default
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*/
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#define PIC1_OFFSET 0x20
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#define PIC2_OFFSET 0x28
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void init_pic(void)
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{
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unsigned char a1, a2;
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a1 = inb(PIC1_DATA); // save masks
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a2 = inb(PIC2_DATA);
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outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4); // starts the initialization sequence (in cascade mode)
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io_wait();
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outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
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io_wait();
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outb(PIC1_DATA, PIC1_OFFSET); // ICW2: Master PIC vector offset
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io_wait();
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outb(PIC2_DATA, PIC2_OFFSET); // ICW2: Slave PIC vector offset
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io_wait();
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outb(PIC1_DATA, 4); // ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100)
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io_wait();
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outb(PIC2_DATA, 2); // ICW3: tell Slave PIC its cascade identity (0000 0010)
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io_wait();
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outb(PIC1_DATA, ICW4_8086);
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io_wait();
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outb(PIC2_DATA, ICW4_8086);
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io_wait();
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outb(PIC1_DATA, a1); // restore saved masks.
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outb(PIC2_DATA, a2);
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}
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void pic_clear_mask(uint8_t irq) {
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uint16_t port;
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uint8_t value;
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if(irq < 8) {
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port = PIC1_DATA;
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} else {
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port = PIC2_DATA;
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irq -= 8;
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}
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value = inb(port) & ~(1 << irq);
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outb(port, value);
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}
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void pic_set_mask(uint8_t irq) {
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uint16_t port;
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uint8_t value;
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if(irq < 8) {
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port = PIC1_DATA;
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} else {
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port = PIC2_DATA;
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irq -= 8;
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}
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value = inb(port) | (1 << irq);
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outb(port, value);
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}
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