f1923fdbcf
- Reworked IDT initialization to register all 32 CPU exception handlers (ISR 0-31) and 16 hardware interrupt handlers (IRQ 0-15, mapped to IDT entries 32-47). - Created assembly stubs in interrupts.S using macros for ISRs with and without error codes, plus IRQ stubs. All route through a common stub that saves registers, loads kernel data segment, and calls the C handler. - Added isr.c with a unified interrupt dispatcher that handles both exceptions (halts on fault) and hardware IRQs (sends EOI via PIC). - Implemented PIC (8259) driver in pic.c with full initialization sequence that remaps IRQ 0-7 to IDT 32-39 and IRQ 8-15 to IDT 40-47. Includes mask/unmask and EOI support. - Extracted port I/O primitives (inb, outb, io_wait) into port_io.h header for reuse across drivers. - Kernel now initializes PIC after IDT and enables interrupts with STI.
19 lines
524 B
C
19 lines
524 B
C
#ifndef ISR_H
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#define ISR_H
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#include <stdint.h>
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typedef struct registers
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{
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uint32_t ds; // Data segment selector
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uint32_t edi, esi, ebp, esp, ebx, edx, ecx, eax; // Pushed by pusha
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uint32_t int_no, err_code; // Interrupt number and error code (if applicable)
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uint32_t eip, cs, eflags, useresp, ss; // Pushed by the processor automatically
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} registers_t;
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typedef void (*isr_t)(registers_t*);
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void isr_handler(registers_t* regs);
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#endif
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