f1923fdbcf
- Reworked IDT initialization to register all 32 CPU exception handlers (ISR 0-31) and 16 hardware interrupt handlers (IRQ 0-15, mapped to IDT entries 32-47). - Created assembly stubs in interrupts.S using macros for ISRs with and without error codes, plus IRQ stubs. All route through a common stub that saves registers, loads kernel data segment, and calls the C handler. - Added isr.c with a unified interrupt dispatcher that handles both exceptions (halts on fault) and hardware IRQs (sends EOI via PIC). - Implemented PIC (8259) driver in pic.c with full initialization sequence that remaps IRQ 0-7 to IDT 32-39 and IRQ 8-15 to IDT 40-47. Includes mask/unmask and EOI support. - Extracted port I/O primitives (inb, outb, io_wait) into port_io.h header for reuse across drivers. - Kernel now initializes PIC after IDT and enables interrupts with STI.
26 lines
540 B
C
26 lines
540 B
C
#ifndef PORT_IO_H
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#define PORT_IO_H
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#include <stdint.h>
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static inline void outb(uint16_t port, uint8_t val)
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{
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asm volatile ( "outb %b0, %w1" : : "a"(val), "Nd"(port) );
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}
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static inline uint8_t inb(uint16_t port)
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{
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uint8_t ret;
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asm volatile ( "inb %w1, %b0" : "=a"(ret) : "Nd"(port) );
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return ret;
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}
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static inline void io_wait(void)
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{
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/* Port 0x80 is used for 'checkpoints' during POST. */
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/* The Linux kernel seems to think it is free for use :-/ */
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asm volatile ( "outb %%al, $0x80" : : "a"(0) );
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}
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#endif
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