- Created src/e3c509.h: full windowed register model (8 windows),
command codes, status/interrupt bits, RX filter, transceiver types,
device struct and API declarations
- Created src/e3c509.c: full driver implementation with PIO TX/RX,
window selection, 10base-T (RJ45) transceiver config, MAC address
read from Window 2, FIFO-based packet send/receive, IRQ handler,
devicefs char device registration as 'eth' class
- Probe uses manufacturer ID check (0x6D50 at Window 0)
- Only 10base-T supported per design requirements
- Wired IRQ 10 (vector 42) handler into isr.c
- QEMU does not emulate 3C509 ISA, so driver correctly probes
'not found' in QEMU; tested alongside NE2000 without issues
Add a driver for NE2000-compatible ISA Ethernet cards based on the
DP8390 controller. Features:
- PROM-based MAC address detection and validation
- Programmed I/O (PIO) remote DMA for data transfers
- Ring buffer management for RX with wrap-around handling
- IRQ 9-driven packet reception and transmission
- Synchronous TX with timeout
- Character device registration as 'eth' class (/dev/ethN)
Probe verifies card presence by resetting the controller, configuring
it for PROM reading, and checking the MAC is not all-0xFF/all-0x00
(which would indicate no hardware at the I/O base).
NE2000 memory layout (16 KiB on-card RAM):
- Pages 0x40-0x45: TX buffer (1536 bytes, 1 MTU frame)
- Pages 0x46-0x7F: RX ring buffer (~14.5 KiB)
Tested with QEMU: `-device ne2k_isa,iobase=0x300,irq=9` correctly
detects the card and registers /dev/eth1. Without the NIC option,
probe correctly reports 'not found'.
Add Intel 82077AA-compatible floppy disk controller driver with:
- CMOS-based drive detection (register 0x10)
- FDC reset with DOR toggle and SPECIFY command
- Motor control with spin-up delay
- ISA DMA channel 2 setup for data transfers
- LBA-to-CHS conversion for 1.44MB geometry
- Single-sector read/write via DMA with 7-byte result phase
- Seek and recalibrate with sense interrupt verification
- IRQ 6 handler (vector 38) for command completion
- Devicefs integration as 'floppy' class block devices
The IRQ wait function detects whether interrupts are enabled
(EFLAGS IF bit) and temporarily enables them if needed, allowing
the driver to work during early init before the kernel calls STI.
The scheduler safely handles timer interrupts in this window since
no user processes exist yet.
Tested with QEMU: drive detected as 1.44M 3.5", registered as
/dev/floppy1, full boot succeeds with CD+HDD+floppy attached.
Add complete user-mode process support:
- TSS (tss.c/h): Task State Segment for Ring 3->0 transitions, installed
as GDT entry 5 (selector 0x28). ESP0 updated per-process for kernel
stack switching.
- Process management (process.c/h): Process table with up to 64 processes.
process_create() clones kernel page directory, maps user code at
0x08048000 and user stack at 0xBFFFF000, copies flat binary code.
Round-robin scheduler via schedule_tick() modifies the interrupt frame
in-place for zero-copy context switching.
- System calls (syscall.c/h): INT 0x80 dispatcher with 8 syscalls:
SYS_EXIT, SYS_WRITE (to debug port + VGA), SYS_READ, SYS_FORK,
SYS_GETPID, SYS_YIELD, SYS_WAITPID, SYS_EXEC. IDT gate at 0x80
uses DPL=3 (flags 0xEE) so user code can invoke it.
- Assembly stubs (interrupts.S): isr128 for INT 0x80, tss_flush for
loading the Task Register, enter_usermode for initial iret to Ring 3.
- Paging extensions (paging.c/h): paging_clone_directory() to create
per-process page directories, paging_map_page_in() for mapping into
non-active directories, paging_switch_directory() for CR3 switching.
- GDT expanded from 5 to 6 entries to accommodate TSS descriptor.
gdt_set_gate() exposed in header for TSS initialization.
- ISR handler routes timer IRQ (32) to scheduler and INT 0x80 to
syscall dispatcher. Exception handler now prints EIP/CS/ERR for
debugging.
- Kernel boots a test user program that writes 'Hello from Ring 3!'
via SYS_WRITE and exits with code 42 via SYS_EXIT. Verified working
in QEMU.
Context switching approach: Timer/syscall interrupts save all registers
via the ISR stub. schedule_tick() copies saved_regs between PCBs and
overwrites the interrupt frame, so the existing iret restores the next
process's state without separate switch assembly.
- Reworked IDT initialization to register all 32 CPU exception handlers (ISR 0-31)
and 16 hardware interrupt handlers (IRQ 0-15, mapped to IDT entries 32-47).
- Created assembly stubs in interrupts.S using macros for ISRs with and without
error codes, plus IRQ stubs. All route through a common stub that saves
registers, loads kernel data segment, and calls the C handler.
- Added isr.c with a unified interrupt dispatcher that handles both exceptions
(halts on fault) and hardware IRQs (sends EOI via PIC).
- Implemented PIC (8259) driver in pic.c with full initialization sequence that
remaps IRQ 0-7 to IDT 32-39 and IRQ 8-15 to IDT 40-47. Includes mask/unmask
and EOI support.
- Extracted port I/O primitives (inb, outb, io_wait) into port_io.h header for
reuse across drivers.
- Kernel now initializes PIC after IDT and enables interrupts with STI.
