Implement NE2000 ISA Ethernet NIC driver (AI)
Add a driver for NE2000-compatible ISA Ethernet cards based on the DP8390 controller. Features: - PROM-based MAC address detection and validation - Programmed I/O (PIO) remote DMA for data transfers - Ring buffer management for RX with wrap-around handling - IRQ 9-driven packet reception and transmission - Synchronous TX with timeout - Character device registration as 'eth' class (/dev/ethN) Probe verifies card presence by resetting the controller, configuring it for PROM reading, and checking the MAC is not all-0xFF/all-0x00 (which would indicate no hardware at the I/O base). NE2000 memory layout (16 KiB on-card RAM): - Pages 0x40-0x45: TX buffer (1536 bytes, 1 MTU frame) - Pages 0x46-0x7F: RX ring buffer (~14.5 KiB) Tested with QEMU: `-device ne2k_isa,iobase=0x300,irq=9` correctly detects the card and registers /dev/eth1. Without the NIC option, probe correctly reports 'not found'.
This commit is contained in:
AI
30
build.log
30
build.log
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[ 3%] Building user-mode applications
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Building app: cat
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Built: /workspaces/claude-os/build/apps_bin/cat (310 bytes)
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@@ -28,11 +33,23 @@ Building app: sh
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| ^~~~
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1 warning generated.
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Built: /workspaces/claude-os/build/apps_bin/sh (3428 bytes)
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make[2]: Warning: File 'src/CMakeFiles/kernel.dir/build.make' has modification time 48529 s in the future
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[ 9%] Building C object src/CMakeFiles/kernel.dir/ne2000.c.o
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[100%] Generating bootable ISO image
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xorriso 1.5.6 : RockRidge filesystem manipulator, libburnia project.
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Media current: stdio file, overwriteable
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Added to ISO image: directory '/'='/tmp/grub.bEiDnH'
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xorriso : UPDATE : 581 files added in 1 seconds
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xorriso : NOTE : Copying to System Area: 512 bytes from file '/usr/lib/grub/i386-pc/boot_hybrid.img'
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xorriso : UPDATE : Thank you for being patient. Working since 0 seconds.
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Writing to 'stdio:/workspaces/claude-os/release/claude-os.iso' completed successfully.
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@@ -25,6 +25,7 @@ add_executable(kernel
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mbr.c
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fat32.c
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floppy.c
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ne2000.c
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env.c
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keyboard.c
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interrupts.S
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@@ -4,6 +4,7 @@
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#include "syscall.h"
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#include "keyboard.h"
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#include "floppy.h"
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#include "ne2000.h"
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#include <stdint.h>
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/* Forward declaration for kernel panic or similar */
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@@ -68,6 +69,9 @@ void isr_handler(registers_t *regs)
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} else if (regs->int_no == 38) {
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/* Floppy IRQ */
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floppy_irq();
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} else if (regs->int_no == 41) {
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/* NE2000 Ethernet IRQ (IRQ 9, vector 41) */
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ne2k_irq();
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}
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return;
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}
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568
src/ne2000.c
Normal file
568
src/ne2000.c
Normal file
@@ -0,0 +1,568 @@
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/**
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* @file ne2000.c
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* @brief NE2000-compatible ISA Ethernet NIC driver implementation.
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*
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* Drives NE2000-compatible NICs based on the DP8390 Ethernet controller.
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* Uses programmed I/O (PIO) remote DMA for data transfer and IRQ-driven
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* packet reception.
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*
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* The driver probes I/O base 0x300 by performing a reset and checking
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* the ISR reset bit. It reads the MAC address from the card's PROM
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* (first 6 bytes of on-card memory), configures the TX and RX ring
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* buffers, and registers as a character device with devicefs.
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*
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* NE2000 memory layout (16 KiB, 64 pages of 256 bytes):
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* Pages 0x40-0x45: TX buffer (1536 bytes, holds 1 MTU frame)
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* Pages 0x46-0x7F: RX ring buffer (~14.5 KiB)
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*/
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#include "ne2000.h"
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#include "port_io.h"
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#include "pic.h"
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#include "devicefs.h"
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#include "driver.h"
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#include <string.h>
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/* Debug print helpers defined in kernel.c */
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extern void offset_print(const char *str);
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extern void print_hex(uint32_t val);
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/* ================================================================
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* Global state
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* ================================================================ */
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/** Single NE2000 device (we only support one for now). */
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static ne2k_device_t ne2k_dev;
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/** Volatile flag set by IRQ handler when a packet arrives. */
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static volatile int ne2k_rx_ready = 0;
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/** Volatile flag set by IRQ handler when transmit completes. */
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static volatile int ne2k_tx_done = 0;
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/* ================================================================
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* Register access helpers
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* ================================================================ */
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/** Write to a NE2000 register. */
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static inline void ne2k_write(uint16_t base, uint8_t reg, uint8_t val) {
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outb(base + reg, val);
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}
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/** Read from a NE2000 register. */
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static inline uint8_t ne2k_read(uint16_t base, uint8_t reg) {
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return inb(base + reg);
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}
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/**
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* Select a register page (0, 1, or 2).
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* Preserves the STA/STP and RD bits.
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*/
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static void ne2k_page(uint16_t base, uint8_t page) {
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uint8_t cr = ne2k_read(base, NE2K_CR);
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cr = (cr & ~(CR_PS0 | CR_PS1)) | ((page & 0x03) << 6);
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ne2k_write(base, NE2K_CR, cr);
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}
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/* ================================================================
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* Remote DMA (PIO) operations
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* ================================================================ */
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/**
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* Read bytes from the NE2000's on-card memory via remote DMA.
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*
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* @param base I/O base address.
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* @param src Source address in card memory (byte address).
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* @param dst Destination buffer in system RAM.
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* @param len Number of bytes to read.
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*/
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static void ne2k_dma_read(uint16_t base, uint16_t src, void *dst, uint16_t len) {
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ne2k_write(base, NE2K_CR, CR_STA | CR_DMA_ABORT);
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/* Set remote DMA byte count */
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ne2k_write(base, NE2K_RBCR0, (uint8_t)(len & 0xFF));
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ne2k_write(base, NE2K_RBCR1, (uint8_t)((len >> 8) & 0xFF));
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/* Set remote DMA start address */
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ne2k_write(base, NE2K_RSAR0, (uint8_t)(src & 0xFF));
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ne2k_write(base, NE2K_RSAR1, (uint8_t)((src >> 8) & 0xFF));
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/* Start remote DMA read */
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ne2k_write(base, NE2K_CR, CR_STA | CR_DMA_READ);
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/* Read data from data port */
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uint8_t *buf = (uint8_t *)dst;
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uint16_t words = len / 2;
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for (uint16_t i = 0; i < words; i++) {
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uint16_t w = inw(base + NE2K_DATA);
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buf[i * 2] = (uint8_t)(w & 0xFF);
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buf[i * 2 + 1] = (uint8_t)((w >> 8) & 0xFF);
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}
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if (len & 1) {
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uint16_t w = inw(base + NE2K_DATA);
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buf[len - 1] = (uint8_t)(w & 0xFF);
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}
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/* Wait for DMA complete */
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int timeout = 100000;
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while (!(ne2k_read(base, NE2K_ISR) & ISR_RDC) && --timeout > 0);
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/* Acknowledge RDC */
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ne2k_write(base, NE2K_ISR, ISR_RDC);
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}
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/**
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* Write bytes to the NE2000's on-card memory via remote DMA.
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*
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* @param base I/O base address.
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* @param dst Destination address in card memory (byte address).
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* @param src Source buffer in system RAM.
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* @param len Number of bytes to write.
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*/
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static void ne2k_dma_write(uint16_t base, uint16_t dst, const void *src,
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uint16_t len) {
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ne2k_write(base, NE2K_CR, CR_STA | CR_DMA_ABORT);
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/* Set remote DMA byte count */
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ne2k_write(base, NE2K_RBCR0, (uint8_t)(len & 0xFF));
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ne2k_write(base, NE2K_RBCR1, (uint8_t)((len >> 8) & 0xFF));
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/* Set remote DMA start address */
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ne2k_write(base, NE2K_RSAR0, (uint8_t)(dst & 0xFF));
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ne2k_write(base, NE2K_RSAR1, (uint8_t)((dst >> 8) & 0xFF));
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/* Start remote DMA write */
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ne2k_write(base, NE2K_CR, CR_STA | CR_DMA_WRITE);
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/* Write data to data port */
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const uint8_t *buf = (const uint8_t *)src;
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uint16_t words = len / 2;
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for (uint16_t i = 0; i < words; i++) {
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uint16_t w = (uint16_t)buf[i * 2] | ((uint16_t)buf[i * 2 + 1] << 8);
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outw(base + NE2K_DATA, w);
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}
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if (len & 1) {
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outw(base + NE2K_DATA, (uint16_t)buf[len - 1]);
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}
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/* Wait for DMA complete */
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int timeout = 100000;
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while (!(ne2k_read(base, NE2K_ISR) & ISR_RDC) && --timeout > 0);
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/* Acknowledge RDC */
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ne2k_write(base, NE2K_ISR, ISR_RDC);
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}
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/* ================================================================
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* Packet send / receive
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* ================================================================ */
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int ne2k_send(ne2k_device_t *dev, const void *data, uint32_t len) {
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if (!dev || !dev->present) return -1;
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if (len > ETH_FRAME_MAX) return -1;
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/* Minimum Ethernet frame size is 60 bytes (without CRC) */
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uint32_t send_len = len;
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if (send_len < 60) send_len = 60;
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uint16_t base = dev->io_base;
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/* Write packet to TX buffer on card */
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ne2k_dma_write(base, (uint16_t)(NE2K_TX_START << 8),
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data, (uint16_t)len);
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/* If we need to pad, write zeros for the remaining bytes.
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* For simplicity, the DMA write already handles partial words.
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* The card will transmit send_len bytes from the TX page. */
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/* Set transmit page start */
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ne2k_page(base, 0);
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ne2k_write(base, NE2K_TPSR, NE2K_TX_START);
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ne2k_write(base, NE2K_TBCR0, (uint8_t)(send_len & 0xFF));
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ne2k_write(base, NE2K_TBCR1, (uint8_t)((send_len >> 8) & 0xFF));
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/* Trigger transmit */
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ne2k_tx_done = 0;
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ne2k_write(base, NE2K_CR, CR_STA | CR_TXP | CR_DMA_ABORT);
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/* Wait for transmit completion (with timeout) */
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int timeout = 1000000;
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while (!ne2k_tx_done && --timeout > 0) {
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asm volatile("pause");
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}
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if (timeout == 0) {
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offset_print(" NE2K: tx timeout\n");
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return -1;
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}
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return 0;
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}
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int ne2k_recv(ne2k_device_t *dev, void *buf, uint32_t bufsize) {
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if (!dev || !dev->present) return -1;
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uint16_t base = dev->io_base;
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/* Check if there's a packet in the ring */
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ne2k_page(base, 1);
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uint8_t curr = ne2k_read(base, NE2K_CURR);
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ne2k_page(base, 0);
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if (dev->next_rx_page == curr) {
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return 0; /* Ring is empty */
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}
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/* Read the 4-byte rx header from the ring */
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ne2k_rx_header_t hdr;
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uint16_t hdr_addr = (uint16_t)(dev->next_rx_page << 8);
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ne2k_dma_read(base, hdr_addr, &hdr, sizeof(hdr));
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/* Sanity check the header */
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uint16_t pkt_len = hdr.length - (uint16_t)sizeof(ne2k_rx_header_t);
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if (pkt_len > ETH_FRAME_MAX || pkt_len == 0) {
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/* Invalid packet, advance pointer and skip */
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dev->next_rx_page = hdr.next_page;
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ne2k_write(base, NE2K_BNRY,
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(dev->next_rx_page == NE2K_RX_START)
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? NE2K_RX_STOP - 1
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: dev->next_rx_page - 1);
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return -1;
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}
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/* Determine how many bytes to copy to caller */
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uint32_t copy_len = pkt_len;
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if (copy_len > bufsize) copy_len = bufsize;
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/* Read packet data (starts after the 4-byte header) */
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uint16_t data_addr = hdr_addr + (uint16_t)sizeof(ne2k_rx_header_t);
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/* Handle ring buffer wrap-around */
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uint16_t ring_end = (uint16_t)(NE2K_RX_STOP << 8);
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uint16_t ring_start = (uint16_t)(NE2K_RX_START << 8);
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if (data_addr + copy_len > ring_end) {
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/* Wraps around */
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uint16_t first_part = ring_end - data_addr;
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ne2k_dma_read(base, data_addr, buf, first_part);
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ne2k_dma_read(base, ring_start,
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(uint8_t *)buf + first_part,
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(uint16_t)(copy_len - first_part));
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} else {
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ne2k_dma_read(base, data_addr, buf, (uint16_t)copy_len);
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}
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/* Advance BNRY to next_page (one behind CURR means buffer is full) */
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dev->next_rx_page = hdr.next_page;
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ne2k_write(base, NE2K_BNRY,
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(dev->next_rx_page == NE2K_RX_START)
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? NE2K_RX_STOP - 1
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: dev->next_rx_page - 1);
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return (int)copy_len;
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}
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/* ================================================================
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* IRQ handler
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* ================================================================ */
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void ne2k_irq(void) {
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if (!ne2k_dev.present) return;
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uint16_t base = ne2k_dev.io_base;
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uint8_t isr = ne2k_read(base, NE2K_ISR);
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if (isr & ISR_PRX) {
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/* Packet received */
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ne2k_rx_ready = 1;
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ne2k_write(base, NE2K_ISR, ISR_PRX);
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}
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if (isr & ISR_PTX) {
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/* Packet transmitted */
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ne2k_tx_done = 1;
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ne2k_write(base, NE2K_ISR, ISR_PTX);
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}
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if (isr & ISR_RXE) {
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/* Receive error */
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ne2k_write(base, NE2K_ISR, ISR_RXE);
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}
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if (isr & ISR_TXE) {
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/* Transmit error */
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ne2k_tx_done = 1; /* Unblock sender even on error */
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ne2k_write(base, NE2K_ISR, ISR_TXE);
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}
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if (isr & ISR_OVW) {
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/* Overflow — need to handle by resetting RX */
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ne2k_write(base, NE2K_ISR, ISR_OVW);
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}
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if (isr & ISR_CNT) {
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/* Counter overflow */
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ne2k_read(base, NE2K_CNTR0);
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ne2k_read(base, NE2K_CNTR1);
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ne2k_read(base, NE2K_CNTR2);
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ne2k_write(base, NE2K_ISR, ISR_CNT);
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}
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}
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/* ================================================================
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* Devicefs character device operations
|
||||
* ================================================================ */
|
||||
|
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/**
|
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* Read from the NE2000 character device.
|
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* Returns one received Ethernet frame.
|
||||
*/
|
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static int32_t ne2k_char_read(void *dev_data, uint32_t size, void *buf) {
|
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ne2k_device_t *dev = (ne2k_device_t *)dev_data;
|
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return (int32_t)ne2k_recv(dev, buf, size);
|
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}
|
||||
|
||||
/**
|
||||
* Write to the NE2000 character device.
|
||||
* Sends an Ethernet frame.
|
||||
*/
|
||||
static int32_t ne2k_char_write(void *dev_data, uint32_t size, const void *buf) {
|
||||
ne2k_device_t *dev = (ne2k_device_t *)dev_data;
|
||||
if (ne2k_send(dev, buf, size) == 0) {
|
||||
return (int32_t)size;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/** Character device operations for NE2000. */
|
||||
static devicefs_char_ops_t ne2k_char_ops = {
|
||||
.read = ne2k_char_read,
|
||||
.write = ne2k_char_write,
|
||||
};
|
||||
|
||||
/* ================================================================
|
||||
* Initialization
|
||||
* ================================================================ */
|
||||
|
||||
/**
|
||||
* Read the MAC address from the NE2000 PROM.
|
||||
*
|
||||
* The first 32 bytes of NE2000's memory contain the PROM data.
|
||||
* In word-wide mode, each MAC byte is duplicated in the high byte,
|
||||
* so the PROM looks like: M0 M0 M1 M1 M2 M2 M3 M3 M4 M4 M5 M5 ...
|
||||
*/
|
||||
static void ne2k_read_mac(uint16_t base, uint8_t *mac) {
|
||||
uint8_t prom[32];
|
||||
ne2k_dma_read(base, 0x0000, prom, 32);
|
||||
|
||||
/* NE2000 duplicates each byte in word mode */
|
||||
mac[0] = prom[0];
|
||||
mac[1] = prom[2];
|
||||
mac[2] = prom[4];
|
||||
mac[3] = prom[6];
|
||||
mac[4] = prom[8];
|
||||
mac[5] = prom[10];
|
||||
}
|
||||
|
||||
/**
|
||||
* Reset and initialize the NE2000 controller.
|
||||
*/
|
||||
static int ne2k_hw_init(uint16_t base) {
|
||||
/* Reset the card: read from RESET port, then write to it */
|
||||
uint8_t tmp = inb(base + NE2K_RESET);
|
||||
outb(base + NE2K_RESET, tmp);
|
||||
|
||||
/* Wait for reset to complete (ISR bit 7 = RST set) */
|
||||
int timeout = 100000;
|
||||
while (!(ne2k_read(base, NE2K_ISR) & ISR_RST) && --timeout > 0);
|
||||
if (timeout == 0) {
|
||||
offset_print(" NE2K: reset timeout\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Acknowledge the reset */
|
||||
ne2k_write(base, NE2K_ISR, 0xFF);
|
||||
|
||||
/* Stop the NIC and abort any DMA */
|
||||
ne2k_write(base, NE2K_CR, CR_STP | CR_DMA_ABORT);
|
||||
|
||||
/* Data Configuration Register:
|
||||
* Word-wide transfers (WTS), normal operation (LS),
|
||||
* FIFO threshold 8 bytes (FT1) */
|
||||
ne2k_write(base, NE2K_DCR, DCR_WTS | DCR_LS | DCR_FT1);
|
||||
|
||||
/* Clear remote byte count registers (required before starting) */
|
||||
ne2k_write(base, NE2K_RBCR0, 0);
|
||||
ne2k_write(base, NE2K_RBCR1, 0);
|
||||
|
||||
/* Receive Configuration: Accept broadcast and physical match */
|
||||
ne2k_write(base, NE2K_RCR, RCR_AB);
|
||||
|
||||
/* Transmit Configuration: internal loopback during init */
|
||||
ne2k_write(base, NE2K_TCR, TCR_LB0);
|
||||
|
||||
/* Set up ring buffer pointers */
|
||||
ne2k_write(base, NE2K_PSTART, NE2K_RX_START);
|
||||
ne2k_write(base, NE2K_PSTOP, NE2K_RX_STOP);
|
||||
ne2k_write(base, NE2K_BNRY, NE2K_RX_START);
|
||||
|
||||
/* Read MAC address from PROM */
|
||||
ne2k_read_mac(base, ne2k_dev.mac);
|
||||
|
||||
/* Switch to page 1 to set PAR (Physical Address) and CURR */
|
||||
ne2k_page(base, 1);
|
||||
ne2k_write(base, NE2K_PAR0, ne2k_dev.mac[0]);
|
||||
ne2k_write(base, NE2K_PAR1, ne2k_dev.mac[1]);
|
||||
ne2k_write(base, NE2K_PAR2, ne2k_dev.mac[2]);
|
||||
ne2k_write(base, NE2K_PAR3, ne2k_dev.mac[3]);
|
||||
ne2k_write(base, NE2K_PAR4, ne2k_dev.mac[4]);
|
||||
ne2k_write(base, NE2K_PAR5, ne2k_dev.mac[5]);
|
||||
|
||||
/* Set current page (next write page for incoming packets) */
|
||||
ne2k_write(base, NE2K_CURR, NE2K_RX_START + 1);
|
||||
ne2k_dev.next_rx_page = NE2K_RX_START + 1;
|
||||
|
||||
/* Set multicast address registers to accept all multicast */
|
||||
for (int i = 0; i < 8; i++) {
|
||||
ne2k_write(base, NE2K_MAR0 + (uint8_t)i, 0xFF);
|
||||
}
|
||||
|
||||
/* Switch back to page 0 */
|
||||
ne2k_page(base, 0);
|
||||
|
||||
/* Clear all pending interrupts */
|
||||
ne2k_write(base, NE2K_ISR, 0xFF);
|
||||
|
||||
/* Enable interrupts: PRX, PTX, RXE, TXE, OVW, CNT */
|
||||
ne2k_write(base, NE2K_IMR, ISR_PRX | ISR_PTX | ISR_RXE |
|
||||
ISR_TXE | ISR_OVW | ISR_CNT);
|
||||
|
||||
/* Take the NIC out of loopback: normal transmit configuration */
|
||||
ne2k_write(base, NE2K_TCR, 0x00);
|
||||
|
||||
/* Start the NIC */
|
||||
ne2k_write(base, NE2K_CR, CR_STA | CR_DMA_ABORT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ================================================================
|
||||
* Driver framework integration
|
||||
* ================================================================ */
|
||||
|
||||
/**
|
||||
* Probe for an NE2000 card at the default I/O base.
|
||||
*
|
||||
* Reset the card, check the ISR reset bit, then verify by reading
|
||||
* the PROM (MAC address). If all bytes are 0xFF or 0x00 there is
|
||||
* no real card at this address.
|
||||
*/
|
||||
static driver_probe_result_t ne2k_probe(void) {
|
||||
uint16_t base = NE2K_DEFAULT_IOBASE;
|
||||
|
||||
/* Try to reset */
|
||||
uint8_t tmp = inb(base + NE2K_RESET);
|
||||
outb(base + NE2K_RESET, tmp);
|
||||
|
||||
/* Brief delay */
|
||||
for (volatile int i = 0; i < 10000; i++) {
|
||||
asm volatile("pause");
|
||||
}
|
||||
|
||||
/* Check if the ISR reset bit is set */
|
||||
uint8_t isr = ne2k_read(base, NE2K_ISR);
|
||||
if (!(isr & ISR_RST)) {
|
||||
return DRIVER_PROBE_NOT_FOUND;
|
||||
}
|
||||
|
||||
/* Acknowledge the reset */
|
||||
ne2k_write(base, NE2K_ISR, 0xFF);
|
||||
|
||||
/* Configure for PROM reading */
|
||||
ne2k_write(base, NE2K_CR, CR_STP | CR_DMA_ABORT);
|
||||
ne2k_write(base, NE2K_DCR, DCR_WTS | DCR_LS | DCR_FT1);
|
||||
ne2k_write(base, NE2K_RBCR0, 0);
|
||||
ne2k_write(base, NE2K_RBCR1, 0);
|
||||
ne2k_write(base, NE2K_RCR, RCR_MON);
|
||||
ne2k_write(base, NE2K_TCR, TCR_LB0);
|
||||
ne2k_write(base, NE2K_PSTART, NE2K_RX_START);
|
||||
ne2k_write(base, NE2K_PSTOP, NE2K_RX_STOP);
|
||||
ne2k_write(base, NE2K_BNRY, NE2K_RX_START);
|
||||
|
||||
/* Read 32 bytes of PROM data */
|
||||
uint8_t prom[32];
|
||||
ne2k_dma_read(base, 0x0000, prom, 32);
|
||||
|
||||
/* Validate: the MAC should not be all 0xFF or all 0x00 */
|
||||
int all_ff = 1, all_00 = 1;
|
||||
for (int i = 0; i < 12; i += 2) {
|
||||
if (prom[i] != 0xFF) all_ff = 0;
|
||||
if (prom[i] != 0x00) all_00 = 0;
|
||||
}
|
||||
|
||||
if (all_ff || all_00) {
|
||||
return DRIVER_PROBE_NOT_FOUND;
|
||||
}
|
||||
|
||||
return DRIVER_PROBE_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the NE2000 driver.
|
||||
*/
|
||||
static int ne2k_driver_init(void) {
|
||||
memset(&ne2k_dev, 0, sizeof(ne2k_dev));
|
||||
|
||||
ne2k_dev.io_base = NE2K_DEFAULT_IOBASE;
|
||||
ne2k_dev.irq = NE2K_DEFAULT_IRQ;
|
||||
|
||||
/* Enable IRQ in PIC */
|
||||
pic_clear_mask(ne2k_dev.irq);
|
||||
|
||||
/* Initialize hardware */
|
||||
if (ne2k_hw_init(ne2k_dev.io_base) != 0) {
|
||||
offset_print(" NE2K: initialization failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
ne2k_dev.present = 1;
|
||||
|
||||
/* Print MAC address */
|
||||
offset_print(" NE2K: MAC ");
|
||||
for (int i = 0; i < 6; i++) {
|
||||
if (i > 0) offset_print(":");
|
||||
print_hex(ne2k_dev.mac[i]);
|
||||
}
|
||||
offset_print("\n");
|
||||
|
||||
/* Register as character device */
|
||||
devicefs_register_char("eth", &ne2k_char_ops, &ne2k_dev);
|
||||
|
||||
offset_print(" NE2K: initialized on I/O ");
|
||||
print_hex(ne2k_dev.io_base);
|
||||
offset_print(" IRQ ");
|
||||
print_hex(ne2k_dev.irq);
|
||||
offset_print("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
ne2k_device_t *ne2k_get_device(void) {
|
||||
return ne2k_dev.present ? &ne2k_dev : NULL;
|
||||
}
|
||||
|
||||
int ne2k_init(void) {
|
||||
return ne2k_driver_init();
|
||||
}
|
||||
|
||||
/* ================================================================
|
||||
* Driver registration
|
||||
* ================================================================ */
|
||||
|
||||
static const driver_t ne2k_driver = {
|
||||
.name = "ne2000",
|
||||
.probe = ne2k_probe,
|
||||
.init = ne2k_driver_init,
|
||||
};
|
||||
|
||||
REGISTER_DRIVER(ne2k_driver);
|
||||
221
src/ne2000.h
Normal file
221
src/ne2000.h
Normal file
@@ -0,0 +1,221 @@
|
||||
/**
|
||||
* @file ne2000.h
|
||||
* @brief NE2000-compatible ISA Ethernet NIC driver.
|
||||
*
|
||||
* Drives NE2000-compatible NICs based on the DP8390 Ethernet chip.
|
||||
* The driver probes I/O base 0x300 (the common default) and uses
|
||||
* IRQ 9 for interrupt-driven packet reception.
|
||||
*
|
||||
* Packets are stored in the card's internal 16 KiB RAM using a
|
||||
* ring buffer. The driver transmits packets synchronously.
|
||||
*
|
||||
* The NE2000 registers with the devicefs as a character device
|
||||
* (named "eth1", "eth2", etc.) for the ethernet subsystem to use.
|
||||
*/
|
||||
|
||||
#ifndef NE2000_H
|
||||
#define NE2000_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* ================================================================
|
||||
* NE2000 I/O Port Layout (offsets from base)
|
||||
*
|
||||
* The DP8390 has 3 register pages selected by bits 6-7 of the
|
||||
* Command register (offset 0x00).
|
||||
* ================================================================ */
|
||||
|
||||
/** Default ISA I/O base for NE2000. */
|
||||
#define NE2K_DEFAULT_IOBASE 0x300
|
||||
|
||||
/** Default ISA IRQ for NE2000. */
|
||||
#define NE2K_DEFAULT_IRQ 9
|
||||
|
||||
/* --- Shared registers (all pages) --- */
|
||||
#define NE2K_CR 0x00 /**< Command register */
|
||||
|
||||
/* --- Page 0 read registers --- */
|
||||
#define NE2K_CLDA0 0x01 /**< Current Local DMA Address 0 */
|
||||
#define NE2K_CLDA1 0x02 /**< Current Local DMA Address 1 */
|
||||
#define NE2K_BNRY 0x03 /**< Boundary pointer (last read page) */
|
||||
#define NE2K_TSR 0x04 /**< Transmit Status Register */
|
||||
#define NE2K_NCR 0x05 /**< Number of Collisions Register */
|
||||
#define NE2K_FIFO 0x06 /**< FIFO */
|
||||
#define NE2K_ISR 0x07 /**< Interrupt Status Register */
|
||||
#define NE2K_CRDA0 0x08 /**< Current Remote DMA Address 0 */
|
||||
#define NE2K_CRDA1 0x09 /**< Current Remote DMA Address 1 */
|
||||
#define NE2K_RSR 0x0C /**< Receive Status Register */
|
||||
#define NE2K_CNTR0 0x0D /**< Tally Counter 0 (frame alignment errors) */
|
||||
#define NE2K_CNTR1 0x0E /**< Tally Counter 1 (CRC errors) */
|
||||
#define NE2K_CNTR2 0x0F /**< Tally Counter 2 (missed packets) */
|
||||
|
||||
/* --- Page 0 write registers --- */
|
||||
#define NE2K_PSTART 0x01 /**< Page Start (rx ring start, in pages) */
|
||||
#define NE2K_PSTOP 0x02 /**< Page Stop (rx ring end, in pages) */
|
||||
/* BNRY = 0x03 shared */
|
||||
#define NE2K_TPSR 0x04 /**< Transmit Page Start */
|
||||
#define NE2K_TBCR0 0x05 /**< Transmit Byte Count 0 */
|
||||
#define NE2K_TBCR1 0x06 /**< Transmit Byte Count 1 */
|
||||
/* ISR = 0x07 shared */
|
||||
#define NE2K_RSAR0 0x08 /**< Remote Start Address 0 */
|
||||
#define NE2K_RSAR1 0x09 /**< Remote Start Address 1 */
|
||||
#define NE2K_RBCR0 0x0A /**< Remote Byte Count 0 */
|
||||
#define NE2K_RBCR1 0x0B /**< Remote Byte Count 1 */
|
||||
#define NE2K_RCR 0x0C /**< Receive Configuration Register */
|
||||
#define NE2K_TCR 0x0D /**< Transmit Configuration Register */
|
||||
#define NE2K_DCR 0x0E /**< Data Configuration Register */
|
||||
#define NE2K_IMR 0x0F /**< Interrupt Mask Register */
|
||||
|
||||
/* --- Page 1 registers (r/w) --- */
|
||||
/* NE2K_CR = 0x00 */
|
||||
#define NE2K_PAR0 0x01 /**< Physical Address 0 (MAC byte 0) */
|
||||
#define NE2K_PAR1 0x02
|
||||
#define NE2K_PAR2 0x03
|
||||
#define NE2K_PAR3 0x04
|
||||
#define NE2K_PAR4 0x05
|
||||
#define NE2K_PAR5 0x06
|
||||
#define NE2K_CURR 0x07 /**< Current Page (next rx write page) */
|
||||
#define NE2K_MAR0 0x08 /**< Multicast Address Register 0 */
|
||||
|
||||
/* --- NE2000 data port (offset 0x10) --- */
|
||||
#define NE2K_DATA 0x10 /**< Data port for remote DMA */
|
||||
#define NE2K_RESET 0x1F /**< Reset port */
|
||||
|
||||
/* ================================================================
|
||||
* Command Register (CR) bits
|
||||
* ================================================================ */
|
||||
#define CR_STP 0x01 /**< Stop: software reset */
|
||||
#define CR_STA 0x02 /**< Start: activate NIC */
|
||||
#define CR_TXP 0x04 /**< Transmit Packet */
|
||||
#define CR_RD0 0x08 /**< Remote DMA command bit 0 */
|
||||
#define CR_RD1 0x10 /**< Remote DMA command bit 1 */
|
||||
#define CR_RD2 0x20 /**< Remote DMA command bit 2 (abort/complete) */
|
||||
#define CR_PS0 0x40 /**< Page Select bit 0 */
|
||||
#define CR_PS1 0x80 /**< Page Select bit 1 */
|
||||
|
||||
/** Remote DMA read */
|
||||
#define CR_DMA_READ CR_RD0
|
||||
/** Remote DMA write */
|
||||
#define CR_DMA_WRITE CR_RD1
|
||||
/** Abort/complete remote DMA */
|
||||
#define CR_DMA_ABORT CR_RD2
|
||||
|
||||
/* ================================================================
|
||||
* ISR / IMR bits
|
||||
* ================================================================ */
|
||||
#define ISR_PRX 0x01 /**< Packet Received */
|
||||
#define ISR_PTX 0x02 /**< Packet Transmitted */
|
||||
#define ISR_RXE 0x04 /**< Receive Error */
|
||||
#define ISR_TXE 0x08 /**< Transmit Error */
|
||||
#define ISR_OVW 0x10 /**< Overflow Warning */
|
||||
#define ISR_CNT 0x20 /**< Counter Overflow */
|
||||
#define ISR_RDC 0x40 /**< Remote DMA Complete */
|
||||
#define ISR_RST 0x80 /**< Reset Status */
|
||||
|
||||
/* ================================================================
|
||||
* DCR bits
|
||||
* ================================================================ */
|
||||
#define DCR_WTS 0x01 /**< Word Transfer Select (1=16-bit) */
|
||||
#define DCR_BOS 0x02 /**< Byte Order Select */
|
||||
#define DCR_LAS 0x04 /**< Long Address Select */
|
||||
#define DCR_LS 0x08 /**< Loopback Select (1=normal) */
|
||||
#define DCR_AR 0x10 /**< Auto-initialize Remote */
|
||||
#define DCR_FT0 0x20 /**< FIFO Threshold bit 0 */
|
||||
#define DCR_FT1 0x40 /**< FIFO Threshold bit 1 */
|
||||
|
||||
/* ================================================================
|
||||
* TCR bits
|
||||
* ================================================================ */
|
||||
#define TCR_LB0 0x02 /**< Loopback bit 0 */
|
||||
#define TCR_LB1 0x04 /**< Loopback bit 1 */
|
||||
|
||||
/* ================================================================
|
||||
* RCR bits
|
||||
* ================================================================ */
|
||||
#define RCR_SEP 0x01 /**< Save Errored Packets */
|
||||
#define RCR_AR 0x02 /**< Accept Runt Packets */
|
||||
#define RCR_AB 0x04 /**< Accept Broadcast */
|
||||
#define RCR_AM 0x08 /**< Accept Multicast */
|
||||
#define RCR_PRO 0x10 /**< Promiscuous Mode */
|
||||
#define RCR_MON 0x20 /**< Monitor Mode */
|
||||
|
||||
/* ================================================================
|
||||
* NE2000 ring buffer layout (16 KiB on-card RAM)
|
||||
*
|
||||
* Pages are 256 bytes each. NE2000 has 32 pages (0x40-0x80).
|
||||
* - TX buffer: page 0x40 (room for 1 MTU frame, 6 pages)
|
||||
* - RX ring: pages 0x46-0x80
|
||||
* ================================================================ */
|
||||
#define NE2K_MEM_START 0x40 /**< Start of NE2000 RAM (page number) */
|
||||
#define NE2K_MEM_END 0x80 /**< End of NE2000 RAM (page number, exclusive) */
|
||||
#define NE2K_TX_START 0x40 /**< TX buffer start page */
|
||||
#define NE2K_RX_START 0x46 /**< RX ring start page */
|
||||
#define NE2K_RX_STOP 0x80 /**< RX ring stop page (exclusive) */
|
||||
|
||||
/** Maximum Ethernet frame size. */
|
||||
#define ETH_FRAME_MAX 1518
|
||||
#define ETH_HEADER_SIZE 14
|
||||
|
||||
/* ================================================================
|
||||
* NE2000 received packet header (prepended by the card)
|
||||
* ================================================================ */
|
||||
typedef struct __attribute__((packed)) ne2k_rx_header {
|
||||
uint8_t status; /**< Receive status (matches RSR). */
|
||||
uint8_t next_page; /**< Next packet page pointer. */
|
||||
uint16_t length; /**< Total length including this header. */
|
||||
} ne2k_rx_header_t;
|
||||
|
||||
/* ================================================================
|
||||
* NE2000 device state
|
||||
* ================================================================ */
|
||||
typedef struct ne2k_device {
|
||||
uint16_t io_base; /**< I/O base address. */
|
||||
uint8_t irq; /**< IRQ number. */
|
||||
uint8_t mac[6]; /**< MAC address. */
|
||||
uint8_t next_rx_page; /**< Next page to read from RX ring. */
|
||||
int present; /**< 1 if card detected. */
|
||||
} ne2k_device_t;
|
||||
|
||||
/* ================================================================
|
||||
* Public API
|
||||
* ================================================================ */
|
||||
|
||||
/**
|
||||
* Initialize NE2000 driver.
|
||||
* Called automatically via REGISTER_DRIVER.
|
||||
*/
|
||||
int ne2k_init(void);
|
||||
|
||||
/**
|
||||
* NE2000 IRQ handler.
|
||||
* Called from isr.c when the NE2000 IRQ fires.
|
||||
*/
|
||||
void ne2k_irq(void);
|
||||
|
||||
/**
|
||||
* Send an Ethernet frame.
|
||||
*
|
||||
* @param dev NE2000 device.
|
||||
* @param data Frame data (starting with destination MAC).
|
||||
* @param len Frame length in bytes (max 1518).
|
||||
* @return 0 on success, -1 on failure.
|
||||
*/
|
||||
int ne2k_send(ne2k_device_t *dev, const void *data, uint32_t len);
|
||||
|
||||
/**
|
||||
* Receive a pending Ethernet frame.
|
||||
*
|
||||
* @param dev NE2000 device.
|
||||
* @param buf Buffer for received frame.
|
||||
* @param bufsize Buffer size.
|
||||
* @return Number of bytes received, 0 if no packet, -1 on error.
|
||||
*/
|
||||
int ne2k_recv(ne2k_device_t *dev, void *buf, uint32_t bufsize);
|
||||
|
||||
/**
|
||||
* Get the NE2000 device pointer (for eth subsystem).
|
||||
* @return Pointer to the device struct, or NULL if not present.
|
||||
*/
|
||||
ne2k_device_t *ne2k_get_device(void);
|
||||
|
||||
#endif /* NE2000_H */
|
||||
Reference in New Issue
Block a user