Implement ISR stubs and PIC driver for hardware interrupt handling (AI)

- Reworked IDT initialization to register all 32 CPU exception handlers (ISR 0-31)
  and 16 hardware interrupt handlers (IRQ 0-15, mapped to IDT entries 32-47).
- Created assembly stubs in interrupts.S using macros for ISRs with and without
  error codes, plus IRQ stubs. All route through a common stub that saves
  registers, loads kernel data segment, and calls the C handler.
- Added isr.c with a unified interrupt dispatcher that handles both exceptions
  (halts on fault) and hardware IRQs (sends EOI via PIC).
- Implemented PIC (8259) driver in pic.c with full initialization sequence that
  remaps IRQ 0-7 to IDT 32-39 and IRQ 8-15 to IDT 40-47. Includes mask/unmask
  and EOI support.
- Extracted port I/O primitives (inb, outb, io_wait) into port_io.h header for
  reuse across drivers.
- Kernel now initializes PIC after IDT and enables interrupts with STI.

src/interrupts.S

@@ -2,6 +2,119 @@
 .global idt_load
 .type idt_load, @function
 idt_load:
-    mov 4(%esp), %eax  /* Turn the argument into the EAX register */
-    lidt (%eax)        /* Load the IDT pointer */
+    mov 4(%esp), %eax
+    lidt (%eax)
     ret
+
+/* Common ISR stub */
+isr_common_stub:
+    pusha
+
+    /* Save segment registers */
+    mov %ds, %ax
+    push %eax
+    
+    /* Load kernel data segment */
+    mov $0x10, %ax
+    mov %ax, %ds
+    mov %ax, %es
+    mov %ax, %fs
+    mov %ax, %gs
+
+    /* Push pointer to stack structure as argument for C handler */
+    push %esp
+    call isr_handler
+    add $4, %esp /* Clean up pushed pointer */
+
+    /* Restore segment registers */
+    pop %eax
+    mov %eax, %ds
+    mov %eax, %es
+    mov %eax, %fs
+    mov %eax, %gs
+
+    popa
+    add $8, %esp /* Cleans up error code and ISR number */
+    iret
+
+/* Macro for exceptions with NO Error Code */
+.macro ISR_NOERRCODE num
+.global isr\num
+.type isr\num, @function
+isr\num:
+    cli
+    push $0
+    push $\num
+    jmp isr_common_stub
+.endm
+
+/* Macro for exceptions WITH Error Code */
+.macro ISR_ERRCODE num
+.global isr\num
+.type isr\num, @function
+isr\num:
+    cli
+    push $\num
+    jmp isr_common_stub
+.endm
+
+ISR_NOERRCODE 0
+ISR_NOERRCODE 1
+ISR_NOERRCODE 2
+ISR_NOERRCODE 3
+ISR_NOERRCODE 4
+ISR_NOERRCODE 5
+ISR_NOERRCODE 6
+ISR_NOERRCODE 7
+ISR_ERRCODE   8
+ISR_NOERRCODE 9
+ISR_ERRCODE   10
+ISR_ERRCODE   11
+ISR_ERRCODE   12
+ISR_ERRCODE   13
+ISR_ERRCODE   14
+ISR_NOERRCODE 15
+ISR_NOERRCODE 16
+ISR_ERRCODE   17
+ISR_NOERRCODE 18
+ISR_NOERRCODE 19
+ISR_NOERRCODE 20
+ISR_NOERRCODE 21
+ISR_NOERRCODE 22
+ISR_NOERRCODE 23
+ISR_NOERRCODE 24
+ISR_NOERRCODE 25
+ISR_NOERRCODE 26
+ISR_NOERRCODE 27
+ISR_NOERRCODE 28
+ISR_NOERRCODE 29
+ISR_ERRCODE   30
+ISR_NOERRCODE 31
+/* Macro for IRQs (Hardware Interrupts) */
+.macro ISR_IRQ num, idt_index
+.global irq\num
+.type irq\num, @function
+irq\num:
+    cli
+    push $0
+    push $\idt_index
+    jmp isr_common_stub
+.endm
+
+/* Hardware Interrupts */
+ISR_IRQ 0,  32
+ISR_IRQ 1,  33
+ISR_IRQ 2,  34
+ISR_IRQ 3,  35
+ISR_IRQ 4,  36
+ISR_IRQ 5,  37
+ISR_IRQ 6,  38
+ISR_IRQ 7,  39
+ISR_IRQ 8,  40
+ISR_IRQ 9,  41
+ISR_IRQ 10, 42
+ISR_IRQ 11, 43
+ISR_IRQ 12, 44
+ISR_IRQ 13, 45
+ISR_IRQ 14, 46
+ISR_IRQ 15, 47