generated from archlinux/template
Add bigscreen beyond patch
This commit is contained in:
parent
85574ebd9d
commit
780bfbc85f
4
PKGBUILD
4
PKGBUILD
@ -257,4 +257,8 @@ for _p in "${pkgname[@]}"; do
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}"
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}"
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done
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done
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source+=('bigscreenBeyond.patch')
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sha256sums+=('3a86f2b023e43e91a8cf6367ff8219f73b1ffc78737adef3a9a517b5a2598c96')
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b2sums+=(934a9ccf4f473e3c03d5be116cbae7355e7074313daa271b317869246fa6a20bd043701b92406bad82eec7e80d6a8b78b1c44ef1e79c1ba708b50d6c8c47c4e8)
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# vim:set ts=8 sts=2 sw=2 et:
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# vim:set ts=8 sts=2 sw=2 et:
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185
bigscreenBeyond.patch
Normal file
185
bigscreenBeyond.patch
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@ -0,0 +1,185 @@
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diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
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index 3b4065099..639699e3b 100644
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--- a/drivers/gpu/drm/drm_edid.c
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+++ b/drivers/gpu/drm/drm_edid.c
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@@ -189,6 +189,9 @@ static const struct edid_quirk {
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/* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
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EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
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+ /* Bigscreen Beyond Headset */
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+ EDID_QUIRK('B', 'I', 'G', 0x1234, EDID_QUIRK_NON_DESKTOP),
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+
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/* Valve Index Headset */
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EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
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EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
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From c33583995576e9ac532c4ad9e260324b1c4fa3a3 Mon Sep 17 00:00:00 2001
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From: Yaroslav Bolyukin <iam@lach.pw>
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Date: Sun, 30 Oct 2022 19:04:26 +0100
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Subject: [PATCH 3/3] drm/amd: use fixed dsc bits-per-pixel from edid
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VESA vendor header from DisplayID spec may contain fixed bit per pixel
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rate, it should be respected by drm driver
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Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
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Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
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---
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drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 ++
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drivers/gpu/drm/amd/display/dc/dc_types.h | 3 +++
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2 files changed, 5 insertions(+)
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diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
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index 38d71b5c1f2d..f2467b64268b 100644
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--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
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+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
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@@ -103,6 +103,8 @@ static bool dc_stream_construct(struct dc_stream_state *stream,
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/* EDID CAP translation for HDMI 2.0 */
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stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
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+ stream->timing.dsc_fixed_bits_per_pixel_x16 =
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+ dc_sink_data->edid_caps.dsc_fixed_bits_per_pixel_x16;
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memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
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stream->timing.dsc_cfg.num_slices_h = 0;
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diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
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index dc78e2404b48..65915a10ab48 100644
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--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
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+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
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@@ -231,6 +231,9 @@ struct dc_edid_caps {
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bool edid_hdmi;
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bool hdr_supported;
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+ /* DisplayPort caps */
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+ uint32_t dsc_fixed_bits_per_pixel_x16;
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+
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struct dc_panel_patch panel_patch;
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};
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--
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2.38.1
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diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
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index 3b4065099..15268afa3 100644
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--- a/drivers/gpu/drm/drm_edid.c
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+++ b/drivers/gpu/drm/drm_edid.c
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@@ -6391,7 +6391,7 @@ static void drm_parse_vesa_mso_data(struct drm_connector *connector,
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if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
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return;
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- if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
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+ if (block->num_bytes < 5) {
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drm_dbg_kms(connector->dev,
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"[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
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connector->base.id, connector->name);
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@@ -6414,24 +6414,37 @@ static void drm_parse_vesa_mso_data(struct drm_connector *connector,
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break;
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}
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- if (!info->mso_stream_count) {
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- info->mso_pixel_overlap = 0;
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- return;
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- }
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+ info->mso_pixel_overlap = 0;
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+
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+ if (info->mso_stream_count) {
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+ info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
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+
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+ if (info->mso_pixel_overlap > 8) {
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+ drm_dbg_kms(connector->dev,
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+ "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
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+ connector->base.id, connector->name,
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+ info->mso_pixel_overlap);
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+ info->mso_pixel_overlap = 8;
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+ }
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- info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
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- if (info->mso_pixel_overlap > 8) {
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drm_dbg_kms(connector->dev,
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- "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
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- connector->base.id, connector->name,
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- info->mso_pixel_overlap);
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- info->mso_pixel_overlap = 8;
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+ "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
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+ connector->base.id, connector->name,
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+ info->mso_stream_count, info->mso_pixel_overlap);
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+ }
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+
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+ if (block->num_bytes < 7) {
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+ /* DSC bpp is optional */
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+ return;
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}
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+ info->dp_dsc_bpp = FIELD_GET(DISPLAYID_VESA_DSC_BPP_INT, vesa->dsc_bpp_int) * 16 +
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+ FIELD_GET(DISPLAYID_VESA_DSC_BPP_FRACT, vesa->dsc_bpp_fract);
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+
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drm_dbg_kms(connector->dev,
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- "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
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- connector->base.id, connector->name,
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- info->mso_stream_count, info->mso_pixel_overlap);
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+ "[CONNECTOR:%d:%s] DSC bits per pixel %u\n",
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+ connector->base.id, connector->name,
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+ info->dp_dsc_bpp);
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}
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static void drm_update_mso(struct drm_connector *connector,
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@@ -6479,6 +6492,7 @@ static void drm_reset_display_info(struct drm_connector *connector)
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info->mso_stream_count = 0;
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info->mso_pixel_overlap = 0;
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info->max_dsc_bpp = 0;
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+ info->dp_dsc_bpp = 0;
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kfree(info->vics);
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info->vics = NULL;
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diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
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index fe88d7fc6..1de1d1726 100644
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--- a/include/drm/drm_connector.h
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+++ b/include/drm/drm_connector.h
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@@ -803,6 +803,12 @@ struct drm_display_info {
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*/
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u32 max_dsc_bpp;
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+ /**
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+ * @dp_dsc_bpp: DP Display-Stream-Compression (DSC) timing's target
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+ * DST bits per pixel in 6.4 fixed point format. 0 means undefined
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+ */
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+ u16 dp_dsc_bpp;
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+
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/**
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* @vics: Array of vics_len VICs. Internal to EDID parsing.
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*/
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diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
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index 566497eeb..3a4bd0816 100644
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--- a/drivers/gpu/drm/drm_displayid_internal.h
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+++ b/drivers/gpu/drm/drm_displayid_internal.h
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@@ -131,12 +131,16 @@ struct displayid_detailed_timing_block {
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#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
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#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
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+#define DISPLAYID_VESA_DSC_BPP_INT GENMASK(5, 0)
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+#define DISPLAYID_VESA_DSC_BPP_FRACT GENMASK(3, 0)
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struct displayid_vesa_vendor_specific_block {
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struct displayid_block base;
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u8 oui[3];
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u8 data_structure_type;
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u8 mso;
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+ u8 dsc_bpp_int;
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+ u8 dsc_bpp_fract;
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} __packed;
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/*
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diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
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index 2c36f3d00ca2..322059dca3ae 100644
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--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
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+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
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@@ -122,6 +122,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
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edid_caps->edid_hdmi = connector->display_info.is_hdmi;
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+ edid_caps->dsc_fixed_bits_per_pixel_x16 = connector->display_info.dp_dsc_bpp;
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+
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apply_edid_quirks(edid_buf, edid_caps);
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sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
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